EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
EDN

New Cypress PREMIS™ 4-PLL Timing Chip Offers Spread Spectrum For Reduced EMI, On-Board Programming For Fast Time-to-Market And Reduced Inventory

New Cypress PREMIS™ 4-PLL Timing Chip Offers Spread Spectrum For Reduced EMI, On-Board Programming For Fast Time-to-Market And Reduced Inventory Cypress Semiconductor Corp. introduced the latest ...
Electronic Design

Bulletproof Your System Timing With Programmable Clocks

Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if ...
Electronic Design

Digital PLL Perks Up Performance In T1-E1, Other TDM Apps

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP ...
Embedded

Mastering motor control: synchronization, timing, and software

Graceful Shutdown: Ensuring the motor and controller are shut down safely when the application is stopped. If the application operates on a multicore MCU/DSP/FPGA, an appropriate inter-core ...