EDN

Opinion: The SoC verification market

Editor's Note: This morning, I received a press release about a company attempting to break in by addressing a new market – that of SoC verification. The body of the release actually tries to explain ...
EDN

Opinion: Lifting the system-level fog with SoC verification

It’s that time of year again, as Design Automation Conference (DAC) begins in a few short days in Fog City, otherwise known as San Francisco. Gary Smith EDA has weighed in once again with a ...
Electronic Design

What’s the Deal with SoC Verification?

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...
Nasdaq

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

Next-generation CXL VIP and System VIP tools provide faster path to testing and compliance with the latest standard SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) ...
Business Wire

Cadence Announces Full DRAM Verification Solution for Automotive, Data Center, and Mobile Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs ...
Embedded

Dealing with SoC hardware/software design complexity with scalable verification methods

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?
Semiconductor Engineering

Verification As A Flow (Part 3)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Semiconductor Engineering

Fast-Track Your Early SoC Design Exploration And Verification

Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as ...
Business Insider

Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Complete range of tests for the entire RISC-V core verification stack from ISA to system-level interaction and performance Test Suite Synthesis AI Technology tracks complex, un-predictable bugs and ...
Electronic Design

Manage ASIC, SoC Design Risk with Leading-Edge Verification Services

Value in design prototyping using FPGAs. Validating the design with firmware. How the process works. Identifying companies with the right experience and expertise in FPGA and design prototyping ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of the industry’s first Verification IP (VIP) and System-Level VIP (System VIP) for the ...