Elektor Academy Pro will host a full-day online conference on 15 April 2026 on the potential of RISC-V-based solutions.
CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software to be available through Intel Pathfinder for RISC-V ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading ...
We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based ...
Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the ...
Another presentation is still being coordinated. More information can be found on the conference website.
This program is a new way for embedded system developers to adopt RISC-V processors faster and with less risk. Catalyst combines CAST’s 32-bit RISC-V processor IP cores with simplified configurations, ...
Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...
BANGKOK, Dec. 12, 2019 /PRNewswire/ -- RISC-V Summit -- The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with ...
SAN MATEO, Calif., Nov. 28, 2017 /PRNewswire/ -- SiFive announced today that it has joined GLOBALFOUNDRIES' FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive's E31 and ...
RISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can use without getting locked into someone else's processor designs ...
RISC-V Inside: DeepComputing recently announced the DC-ROMA RISC-V mainboard, a limited-edition platform providing a unique way to experiment with the RISC-V instruction set. The Chinese company ...
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