System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...

As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs. Designers might hesitate to use ESL because of legacy RTL ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...