Design-Reuse

True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference

True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries. At the 62 nd Design Automation Conference ...
EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
Hackaday

Icestorm Tools Roundup: Open Source FPGA Dev Guide

We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We’ve based several tutorials on the ...
Design-Reuse

ParthusCeva announces extensive upgrade to PLLXpert online and the addition of TSMC 0.13um PLL Compilers

San Jose, Calif - 15 April, 2003. - ParthusCeva, Inc. (NASDAQ: PCVA; LSE: PCV), the industry's leading provider of licensable Digital Signal Processor (DSP) cores and platform-level IP solutions to ...