EDN

PLL combines with digital synthesis

RF synthesis is a critical function in today's electronic communications systems. Two of the technologies used for RF synthesis are phase locked loop (PLL) and direct digital synthesis (DDS). Each has ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 1)

This is Part 1 of a three-part series. As modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher performance than ever before, they’re ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 3)

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 1 of 2)

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...
Hackaday

A PLL For Perfect Pitch

When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...
Business Wire

Silicon Creations Celebrates Milestone with Delivery of 1,000th Production License for Fractional-N PLL

ATLANTA--(BUSINESS WIRE)--Silicon Creations, a leader in high-performance analog and mixed-signal intellectual property (IP), proudly announces the achievement of over 1,000 production licenses for ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...
Design-Reuse

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a ...