SiliconANGLE

New memory architecture targets AI inference bottlenecks

Lightbits Labs Ltd. today is introducing a new architecture aimed at addressing one of the most stubborn bottlenecks in large-scale artificial intelligence inference: the growing mismatch between the ...

XCENA Details MX1 Architecture Integrating Memory Expansion and Near-Memory Computing at Hot Chips 2026

XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, today presented the ...
VentureBeat

Google's new neural-net LLM architecture separates memory components to control exploding costs of capacity and compute

A new neural-network architecture developed by researchers at Google might solve one of the great challenges for large language models (LLMs): extending their memory at inference time without ...
Semiconductor Engineering

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. “Despite decades of ...
Semiconductor Engineering

Reduce Memory Redesigns With Shift-Left

Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals ...