When evaluating a new FPGA architecture, it is important to understand the hardware features and the tradeoffs that can be made in the architecture. Datasheets, user guides, and technical papers on ...

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet ...

SAN FRANCISCO, CA--(Marketwired - Jun 2, 2014) - The who's who of the chip design community will be in San Francisco this week for DAC, and new ideas, trends and technologies will be the talk of the ...

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous ...

As the cost of mask is increasing and the performance gap between FPGA and ASIC is reducing the FPGA is evolving a strong platform for not-only prototyping but also as a platform for real time design.

Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...